Bsrhrki

I read that PLL are used in CPU to generate the clock, but I can't understand why.

I don't really have any guess of why this is.

Been there, done that.

Apart from other reasons mentioned here is a different one:

The marketing guys want to make the chip design as cheap as possible. Thus they prefer to use cheap crystals. The ones use for Ethernet fall in that category. So you often end up having to use a 25MHz crystal.

At the same time marketing want powerful processors. Thus the processor (Let's call it a LEG⁺⁺) should be able to run at 1 or 2 GHz.

The only way to do that is to use a PLL.

Or the processor can run at max 64MHz, but they want to have a USB interface which requires a 48MHz Clock. Again PLL to the rescue.

⁺⁺_{LEG is not a registered trademark. (At least as far as I know)}

PLLs can be used to multiply and divide frequencies. CPUs that have PLLs to generate their clocks are highly reconfigurable. The clock speed can be varied relative to the external reference clock over a wide range, and it's the PLL that makes this possible.

PLLs are used primarily to generate one or more faster or slower clocks from a reference clock.

You might have say a fixed 100MHz crystal, but then want to run your CPU at 2GHz, so a PLL is required to increase the frequency (a 2GHz clock crystal isn't feasible).

Additional you may want to be able to change your CPU frequency on the fly (e.g. a turbo clock). In which case you could have a reconfigurable PLL.

Furthermore you may need a different memory or peripheral clock to your CPU clock. Again a PLL and divider can be used to generate this from a single reference.

3 main reasons;

1) power savings for mobiles and extend CPU life keeping cool.

2) signal integrity is improved using xx multiplier for front side bus due to short wavelength, lower capacitance

3) flexible CPU speeds are possible with throttle on Clock multiplier and Vdd to allow burst CPU power and cool down.

Signal routing of 100MHz FSB is easy, > 1GHz is hard and your CPU is much higher, driver current increases with f and standing wave reflections distort square waves. While reducing CPU clock saves power and reduces temp.

There are several reasons for this. A phase locked loop, or PLL, is a circuit that is used to generate a stable frequency that has a specific mathematical relationship to a reference frequency. Specifically, it is a circuit that is used to control a voltage controlled oscillator (VCO) so that its output is locked into a specific relationship with a reference frequency. It is possible for a PLL to generate a much higher frequency than the reference frequency - for example, a 100 MHz reference can be multiplied up to several GHz. If the PLL is integrated on the same chip where the high frequency output is used, this can save power and reduce EMI by lowering the frequency that is sent through the circuit board traces. Since the relationship is determined with simple frequency dividers, it is very easy to change the output frequency of a PLL by simply changing the divider settings. This can enable power savings using a technique called dynamic frequency scaling, where the frequency is adjusted based on the required processor performance to reduce power consumption.

In a modern CPU, there are going to be multiple PLLs present for providing the clocks for various components. The processing cores themselves will run on one or more clocks that are supplied by one or more PLLs so the core clocks can be adjusted easily. The PCI express interface will also require PLLs, likely multiple PLLs to support operation at different link rates. The memory interface likely requires a different PLL to generate the specific clock frequency that the installed memory requires. All of these PLLs would use the same (relatively) low frequency reference oscillator on the motherboard.